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Corporate Training Topics

RISC-V

RISC-V Advanced Program

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Design For Testability with Lab (Synopsys Tools)

RISC-V RV32I RTL Design using Verilog HDL

This hands-on RISC-V training course covers the RISC-V ISA, pipeline processor RTL design, and implementation using Verilog HDL. You will gain extensive experience in Verilog HDL for RTL synthesis and simulation through various lab exercises. The course culminates in the implementation of a pipeline RISC-V processor in Verilog, following best design, verification practices, and coding standards.
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RISC-V RV32I RTL Verification using UVM

This hands-on RISC-V training course covers the RISC-V ISA, pipeline processor RTL design, and Verilog HDL implementation. You will gain extensive training in Verilog HDL for RTL synthesis and simulation through lab exercises. By the end, you will implement a pipeline RISC-V processor RTL design in Verilog, adhering to best design and verification practices.
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Design For Testability with Lab (Synopsys Tools)

RISC-V RTL Design

This hands-on RISC-V training course covers the RISC-V ISA, pipeline processor RTL design, and RTL verification using UVM. You will gain extensive experience with UVM methodology, applying it to RTL verification through lab exercises and real-time IP and SoC case studies. The course culminates in implementing a UVM class-based verification environment to verify a pipeline RISC-V processor RTL design in Verilog, following best verification practices and coding standards.
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RISC-V instruction set architecture

This RISC-V ISA course provides an in-depth explanation of the RISC-V Instruction Set Architecture, focusing on all RV 32 I instructions with practical examples. The course begins by introducing the need for processors and how various electronic products, such as embedded microcontrollers and SoCs, are built using RISC-V processors. It then covers RISC-V ISA in detail, followed by RISC-V assembly programming. By the end, you’ll be equipped with the knowledge needed for RISC-V processor RTL design.
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ARM

ARM Cortex A - V8 - Software Development

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Design For Testability with Lab (Synopsys Tools)

ARM Cortex A - V7 - Software Development

The ARM V7 architecture forms the foundation of current 32-bit ARM Cortex processors, including Cortex-A9 and A15. This course explores ARM V7 features, ISA, memory mapping, and exception handling.
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AMBA

ARM V7 architecture underpins current 32-bit ARM Cortex processors, like Cortex-A9 and A15. This course covers ARM V7 features, ISA, memory mapping, and exception handling.
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RTL Design

RTL Design Course

This course provides comprehensive coverage of key VLSI topics, including Advanced Digital Design, Verilog HDL, RTL Synthesis with DC Compiler, RTL Linting using Spyglass, SystemVerilog for Design, Equivalence Checking with Formality, Static Timing Analysis using PrimeTime, FPGA fundamentals with Xilinx Vivado ML, Gate Level Simulation (GLS), and Clock Domain Crossing.
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Design For Testability with Lab (Synopsys Tools)

Advanced Digital Design

This Advanced Digital Design course provides an in-depth exploration of digital design principles and static timing analysis. The Digital Design module covers essential concepts such as combinational and sequential logic, FSM (finite state machine) designs, and memory structures. Topics include Logic Gates, Adders, Subtractors, Decoders, Encoders, Multiplexers, Demultiplexers, Flip-Flops, Latches, Counters, Registers, and Memories. In the STA (Static Timing Analysis) module, participants learn the critical importance of timing analysis, including techniques for analyzing both combinational and sequential circuits. The course also delves into strategies to enhance the speed and efficiency of logic circuits.
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Verilog HDL

This hands-on Verilog course provides comprehensive training in coding for both synthesis and simulation. It begins with fundamental concepts of hardware description language, including data types and operators, and advances to more complex topics like assignments, procedural blocks, synthesis coding styles, FSM (finite state machine) coding, and self-checking testbench development. The course includes theory modules, quizzes, lab exercises, and a pilot Verilog RTL project, offering extensive practice in Verilog HDL programming. By the end, you’ll be equipped with practical skills as a proficient Verilog RTL designer.
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Design For Testability with Lab (Synopsys Tools)

RTL Synthesis Using DC Compiler

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RTL Linting using Spyglass

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Equivalence Checking using Formality

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Static Timing Analysis using PrimeTime

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Learning FPGA using Xilinx Vivado ML

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Gate Level Simulation (GLS)

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axi

Clock Domain Crossing

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RTL Verification

RTL Verification Course

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Design For Testability with Lab (Synopsys Tools)

SystemVerilog for Verification Theory & Labs

This hands-on SystemVerilog course thoroughly covers data types and key language concepts, focusing on using these features to build a class-based verification environment. You’ll dive deep into data types, interfaces, object-oriented programming (OOP), randomization, functional coverage, verification planning and management, and testbench architecture. Through extensive lab exercises and practical IP and SoC case studies, the course trains you to create and implement robust class-based verification environments using SystemVerilog.
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Universal Verification Methodology ( UVM ) Theory & Labs

This hands-on UVM course provides a thorough introduction to UVM methodology, covering key concepts like agents, UVCs, AHB UVCs, SoC UVM testbenches, and the UVM testbench framework. You'll explore the base class library, factory, sequences, phases, reporting, TLM ports, virtual sequences, events, callbacks, scoreboards, and UVM environments. Through lab exercises and real-time case studies, including IP and SoC UVM testbenches, you’ll gain practical skills and develop expertise in UVM for functional verification.
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Design For Testability with Lab (Synopsys Tools)

Assertion-based Verification

This hands-on Assertion-Based Verification (ABV) course focuses on using SystemVerilog Assertions (SVA) to verify DUT protocols and functionality. You'll learn about immediate and concurrent assertions, sequences, implication & repetition operators, and writing complex assertions. The course includes labs to reinforce these concepts. Assertions are essential for verifying DUT functionality, debugging simulation failures, and applying formal verification techniques effectively.
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Simulation Debugging using Verdi

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SoC Verification Flow

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Formal Verification using Formality

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Low Power Verification using UPF

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Gate Level Simulation ( GLS) on RISC V

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Physical Design & Verification

Physical Design & Verification Course

This course covers key topics such as RTL Linting and Design Optimization with Fusion Compiler, Static Timing Analysis with PrimeTime, Physical Design using Synopsys ICC2 or Fusion Compiler, and Physical Verification & Sign-off with Siemens Calibre.
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Design For Testability with Lab (Synopsys Tools)

RTL Linting & Design Optimization using Fusion Compiler

Static Timing Analysis (STA) is crucial in ASIC design to ensure timing requirements are met and the design operates at the required clock frequency without setup or hold time violations. This course covers the importance of timing analysis for both combinational and sequential circuits, along with strategies to enhance circuit speed. Starting from the basics, the course progressively leads you to advanced STA concepts.
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Static Timing Analysis using PrimeTime

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Design For Testability with Lab (Synopsys Tools)

Physical Design using Synopsys ICC2 or Fusion Compiler

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Physical Verification & Sign off using Siemens Calibre

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Testing & Timing

Testing & Timing Course

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Design For Testability with Lab (Synopsys Tools)

Static Timing Analysis using PrimeTime

Static Timing Analysis (STA) is crucial in ASIC design to ensure timing requirements are met and the design operates at the required clock frequency without setup or hold time violations. This course covers the importance of timing analysis for both combinational and sequential circuits, along with strategies to enhance circuit speed. Starting from the basics, the course progressively leads you to advanced STA concepts.
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Clock Domain Crossing

In a chip or IP with multiple clocks, clock domain crossing (CDC) happens when data is transferred between flip-flops driven by different clocks. CDC signals originate in one clock domain and are sampled by registers in another. With the increasing complexity of SoCs, featuring multiple clocks for system integration, peripherals, and power management, understanding CDC is essential. This module covers the basics of CDC, how to prevent metastability, the different types of synchronizers, and CDC analysis techniques.
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Design For Testability with Lab (Synopsys Tools)

RTL Linting using Spyglass

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RTL Synthesis Using DC Compiler

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Design for testability - DFT

Design for Testability (DFT) is a critical process in VLSI design to detect manufacturing defects, as fabrication yields are rarely perfect. This course covers the fundamentals of silicon testing and key DFT techniques such as SCAN Insertion, ATPG, JTAG, and BIST. Learners will gain hands-on experience with industry-standard Tessent from Mentor Graphics. Ideal for Electronics Engineers with a solid understanding of Digital Electronics, RTL Design in Verilog HDL, and basic programming skills, this course prepares you to become a skilled DFT Engineer.
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LBIST & MBIST

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Corporate Training Methods

At Quantum Academy, we partner with you to identify your team’s performance goals and align them with our targeted learning tracks and delivery systems. Our customized training methods are designed to inspire, engage, and educate your workforce, ensuring the most effective results for your needs.

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Offline Instructor-Led

Self-paced

Virtual Live Instructor-Led

Blended/Hybrid

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Corporate Training Process

1

Defining Business Objectives

2

Trainee Orientation

3

Structured & Flexible
Daily Planners

4

Access to Learning
Videos

5

24/7 Lab
Access

6

Ongoing
Assessments

7

Reference Materials & Guidance

8

1:1 Lab
Reviews

9

Project Code
Reviews

10

Final
Assessments

11

Specialized Business Communication Sessions

12

Comprehensive Performance Reports

13

Detailed Skill Fit Insights for Project Placement

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