RTL Design using Spyglass & Design Compiler
What you'll learn
CMOS Device and Technology
What you'll learn
Design For Testability with Lab (Synopsys Tools)
What you'll learn
Design Verification with Lab (Synopsys Tools)
What you'll learn
Synthesis, Signoff STA & LEC with Lab (Synopsys Tools)
What you'll learn
RTL Design using Spyglass & Design Compiler
What you'll learn
CMOS Device and Technology
What you'll learn
Physical Design with Lab (Synopsys Tools ICC2)
What you'll learn
Design For Testability with Lab (Synopsys Tools)
What you'll learn
Design Verification with Lab (Synopsys Tools)
What you'll learn
APB Protocol Verification – SV & UVM Based
What you'll learn
AXI-4 Lite Protocol VIP Integration- UVM Based
What you'll learn
Formal Verification
What you'll learn
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Graduate Diploma in FPGA System Design and Verification
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Foundation – Static Timing Analysis
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