About This Course
This comprehensive course at Quantum Academy trains engineers in advanced ASIC verification methodologies. Topics covered include SystemVerilog, UVM (Universal Verification Methodology), Assertion-Based Verification (SVA), Verification Planning and Management, as well as Code and Functional Coverage. Additionally, you’ll gain hands-on experience with Perl scripting to enhance your verification processes. This course is designed to equip you with the skills needed for effective and efficient verification of complex ASIC designs.
What is VLSI VM-PT?
The Advanced ASIC Verification part-time course [VLSI VM-PT] is designed for working professionals who want to enhance their skills and transition into roles as ASIC Verification Engineers. This course provides extensive training in ASIC verification methodologies, helping professionals upgrade their expertise. Key features of the course include advanced Verilog for verification, SystemVerilog, UVM (Universal Verification Methodology), Assertion-Based Verification (SVA), Verification Planning and Management, Code and Functional Coverage, Perl scripting, and VIP coding style.
Why join VLSI VM-PT?
The Advanced ASIC Verification course is a flexible, part-time program designed to fit your schedule and help you either secure a job or advance your career as an ASIC Verification Engineer.
As a verification engineer in the VLSI industry, you’ll need a blend of technical expertise in digital design and verification methodologies, along with strong problem-solving and collaboration skills. With the growing complexity of chip designs, VLSI verification has become a highly specialized field, requiring an in-depth understanding of digital design and advanced verification techniques.
This course provides top-tier training in the latest verification skills, including SystemVerilog, Assertion-Based Verification (SVA/SystemVerilog Assertions), and UVM, all from an industry perspective. By the end of the program, you will be equipped with the practical skills and knowledge needed to become a deployable ASIC Verification Engineer.
Key Features
- Online Course – Verilog – HDL
- Industry-Standard Curriculum
- Blended course with Support Material, Labs, and Projects
- Course Delivered by Industry Experts
- Live Q&A and Review Sessions
- Mobile Apps – Attend Anywhere Anytime
- Certificate on successful completion of the course
- Inexpensive Blended VLSI Courses
VLSI VM-PT Curriculum
The dynamic curriculum of the Advanced ASIC Verification Course is tailored to meet the career goals of working professionals, helping them “future-proof” their skills and stay competitive in the fast-evolving semiconductor technology industry.
Target Audience
- BE/BTech in EEE/ECE/TE/CSE/IT/Instrumentation
- ME/MTech/MS in Electronics/MSc Electronics
Curriculum
Module – 1 | Introduction to Linux
Components of UNIX system
Directory Structure
Utilities and Commands
Vi Editor
Module – 2 | Advanced Verilog for Verification
Tasks and Functions
Delays - Regular, Intra Assignment and Inertial Delays
Race Conditions
File I/O operation
TB Constructs
Self checking Testbenches
Module – 3 | Code Coverage
Statement coverage
Branch Coverage
Expression Coverage
Path Coverage
Toggle Coverage
FSM - State, Transition coverage
Module – 4 | ASIC Verification Methodologies
Directed Vs Random
Functional verification process
Stimulus Generation
Bus functional model
Monitors and reference models
Coverage Driven Verification
Verification Planning and Management
Module – 5 | Introduction to SystemVerilog
Environment Configuration
Reference Models and Predictor Logics
Using Legacy BFMs
Scenario Generation
Testcases - Random, Directed and Corner Case
Coding styles for VIP
Module – 6 | Advanced SystemVerilog
Environment Configuration
Reference Models and Predictor Logics
Using Legacy BFMs
Scenario Generation
Testcases - Random, Directed and Corner Case
Coding styles for VIP
Module – 7 | Verification Planning and Management
Verification Plan
TB Architecture
Coverage Model
Tracking the simulation process
Building regression testsuite
Testsuite optimization
Module – 8 | Assertion Based Verification
Introduction to ABV
Immediate Assertions
Simple Assertions
Sequences
Sequence Composition
Advanced SVA (SystemVerilog Assertions) Features
Assertion Coverage
Module – 9 | UVM – Universal Verification Methodology
Introduction to UVM Methodology
Overview of Project
UVM TB Architecture
Stimulus Modeling
Creating UVCs and Environment
UVM Simulation Phases
Testcase Classes
TLM Overview
Configuring TB Environment
UVM Sequencers
Connecting DUT - Virtual Interface
Virtual Sequences and Sequencers
Creating TB Infrastructure
Connecting multiple UVCs
Building a Scoreboard
Introduction to Register Modeling
Building reusable environments
Module – 10 | Pilot Project – Verification and RTL Sign-Off
Project Specification Analysis
Understanding the architecture
Module-level implementation and verification
Building the top-level module
Module – 11 | RISC V Processor
1. RISC-V Instruction Set Architecture
RISC-V processor overview
RISC-V ISA Overview
RV32I - R and I Type Instruction
RV32I - S and B Type Instructions
RV32I - J and U Type Instructions
RV32I - Assembly Programs
2. RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV321 Instructions Format
RV32I - R and I Type ALU Datapath
RV32I - S Type ALU Datapath - Load and Store
RV32I - B and U Type ALU Datapath
RV32I - J Type ALU Datapath - JAL and JALR
3. RISC-V RV32I 5 stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 stage Pipeline - Data Hazards and Design Approach
RISC-V 5 Stage Pipeline - Control Hazards and Design Approach
Module – 12 | Design Automation using Scripts Perl
Introduction to Perl
Functions and Statements
Numbers, Strings, and Quotes
Comments and Loops
Regular Expressions
File Operations
Module – 13 | Industry Standard Project
Project specification analysis
Defining verification plan
Creating Testbench architecture
Defining Transaction
Implementing the transactors - sequencer, driver, monitor & scoreboard
Implementing the coverage model
Building the top-level verification environment
Defining weighted random, cornercase, and directed
Building the functional and code coverage reports
Module – 14 | Business communication
Transition from College to Corporate
Interpersonal skills and Presentation Skills
Email Etiquette
Resume writing
Mockup Interviews Technical/HR
Interview Skills: Group Discussion and HR Round Preparation
Your Instructors
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