About This Course
About the Course
Dive into the realm of design verification with our comprehensive course, delving into SystemVerilog, UVM, and hands-on projects in APB for thorough testbench creation. Uncover the intricacies of SystemVerilog Object-Oriented Programming (OOPs), Randomization, Inter-process Communication (IPC), and advanced topics in SV and UVM, empowering you to pursue a rewarding career in Design Verification.
Learning Objectives
Apply best practices and knowledge to think through a problem rather than try to memorise the solution.
Be able to identify many electrical and mechanical machines.
Apply engineering concepts across multiple engineering disciplines.
Requirements
- Bring your thinking cap (brain) and I will provide the rest!
Target Audience
- Anyone who is curious about how things work.
- Anyone who loves to learn.
- Anyone who enjoys the gift of knowledge.
- Anyone involved with any engineering related discipline
Curriculum
4 Lessons1h 27m
Design Verification with Lab (Synopsys Tools)
Draft Lesson
Draft Lesson
(Synopsys Tools)
Your Instructors
Google