About This Course
This program offers a comprehensive, hands-on approach to mastering VLSI design along with ASIC and FPGA verification. With practical lab sessions and training on industry-standard protocols, Quantum Academy ensures learners are equipped with real-world skills and technical proficiency required to excel in today’s semiconductor landscape.
What is VLSI RN?
The VLSI RN program at Quantum Academy is a specialized course crafted by seasoned industry professionals to deliver deep, practical training in advanced design and verification techniques. The curriculum covers RTL design, ASIC and FPGA development workflows, FPGA architecture, advanced Verilog for verification, SystemVerilog, UVM, Assertion-Based Verification (SVA), verification planning and strategy, code and functional coverage, Perl scripting, and VIP development methodologies. With this robust training, learners are fully prepared to enter and thrive in the VLSI industry with confidence and cutting-edge skills.
Why join VLSI RN?
- Today’s VLSI chips are marvels of engineering—integrating billions of transistors, millions of logic gates, and substantial memory components for high-speed computation and control.
- But how do engineers successfully design and verify such sophisticated systems?
It takes more than theory—it demands a deep, hands-on mastery of industry-standard tools and techniques, including SoC design, CMOS fundamentals, RTL design, Verilog HDL, FPGA workflows, SystemVerilog, and UVM methodologies. At Quantum Academy, our Advanced VLSI Design and Verification course delivers exclusive, in-demand training in these areas, paired with a structured internship experience. The program is structured with a 30:70 ratio of live instruction to practical application, ensuring learners not only understand the theory but also solidify their skills through real-world lab work and project-based learning.
Blended Course
- 7 Months Training + 5 Months Internship
- Theory & Labs: 5 months online course with daily live Q&A support
- Projects: 2 months, Offline / Online
- Internship: 5 months, Offline / Online
Weekend Course
- 11 Months Training + 5 Months Internship
- Theory & Labs: 9 months, Online course with live Q&A support on weekends
- Projects: 2 months, Offline/Online
- Internship: 5 months, Offline / Online
Offline Course
- 7 Months Training + 5 Months Internship
- Theory & Labs: 5 months, Offline Training
- Projects: 2 months, Offline
- Internship: 5 months, Offline
Online Course
- Theory & Labs: Self-paced
- Projects: Self-paced
- Internship: Self-paced
Key Features
Course Features
- ASIC & FPGA design methodologies
- Training and Internship
- Advanced Logic Design
- Operating System – Linux
- HDL: Verilog
- FPGA Architecture
- RISC-V Instruction Set Architecture
- RISC-V RV32I RTL Architecture Design
- ASIC Verification Methodologies
- HVL: SystemVerilog
- Assertion-Based Verification: SVA
- Universal Verification Methodology – UVM
- Scripting Language: Perl
- Industry Standard Project
- Business Communication
Sample Internship Projects
- RISC-V RTL Design
- AHB2APB Bridge RTL
- PCS Subsystem RTL design
- SPI IP core RTL Design
- UART IP core RTL Design
- RISC-V Verification in UVM
- Bluetooth VIP in UVM
- AHB UVC – Master agent in UVM
- AHB UVC – Slave agent in UVM
- AHB2APB Bridge Verification in UVM
- UART IP Verification in UVM
- PCS subsystem IP Verification – UVM
- AXI UVC – Master agent in UVM
- AXI UVC – Slave agent in UVM
- ICPIT Verification in UVM
- SPI IP Verification – UVM
Elective Module
- DFT – Design For Testability
EDA Tools
- Siemens
- Synopsys
- Xilinx
- Aldec
VLSI RN Curriculum
The dynamic curriculum of the Advance VLSI Design and Verification course fits perfectly with the career aim of fresh engineering graduates and helps them to ‘future-proof’ themselves and remain relevant in the rapidly evolving Semiconductor technology space.
Requirements
- BE/BTech in EEE/ECE/TE/CSE/IT/ Instrumentation
- ME/MTech/MS in Electronics/MSc Electronics
Curriculum
5113h
Introduction to VLSI
VLSI Design Flow
ASIC vs FPGA
RTL Design Methodologies
Introduction to ASIC Verification Methodologies
VLSI Design Flow Steps - Demo
Introduction to Linux
Components of the UNIX system
Directory Structure
Utilities and Commands
Vi Editor
Advanced Digital Design
Introduction to Digital Electronics
Arithmetic Circuits
Data processing Circuits
Universal Logic Elements
Combinational Circuits - Design and Analysis
Latches and Flip flops
Shift Registers and Counters
Sequential Circuits - Design and Analysis
Memories and PLD
Finite State Machine
Microcontroller Design
Verilog HDL – RTL Coding and Synthesis
1. Introduction to Verilog HDL
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
2. Data Types
- Type Concept
- Nets and registers
- Non-hardware equivalent variables
- Arrays
3. Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional operators
- Relational and arithmetic operators
- Shift and Equality operators
- Operators precedence
4. Assignments
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
5. Finite State Machine
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
6. Advanced Verilog for Verification
- System Tasks
- Compiler directives
- Internal variable monitoring
- File input and output
7. Synthesis Coding
- Unwanted latches
- Synthesizable operators
- RTL Coding styles
- Synthesis errors
Static Timing Analysis
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Methods to improve timing
FPGA Architecture
1. PLD
- General Structure and Classification
- CPLD Vs FPGA
2. Xilinx CPLD - Xc9500
- Block Diagram of CPLD
- Detailed study of each block
- Timing Model
3. Xilinx FPGA
- FPGA Architecture
- CLBs and Input/Output Blocks
- Luts, SLICE DFFs
- Dedicated MUXes
- Programmable Interconnects
- Architectural Resources
- Power Distribution and Configuration
4. FPGA Architecture of Different Xilinx Families
Code Coverage
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM - State, Transition coverage
Verilog Mini Project RTL Coding and Synthesis
- Project Specification Analysis
- Understanding the architecture
- Module-level implementation and verification
- Building the top-level module
CMOS Fundamentals
- Non-Ideal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS circuit design
- Fabricaion Process Overview
- Transistor sizing
- Layout and Stick Diagrams
- CMOS Technology - Current Trends
- CMOS Processing Steps
Design Automation using Scripts Perl
- Introduction to Perl
- Functions and Statements
- Numbers, Strings, and Quotes
- Comments and Loops
- Regular Expressions
- File Operations
ASIC Verification Methodologies
- Directed Vs Random
- Functional verification process
- Monitors and reference models
- Stimulus Generation
- Verification Planning and management
- Bus functional model
- Coverage Driven Verification
SystemVerilog HVL
1. Introduction to SystemVerilog
- New Data types
- Tasks and Functions
- Interfaces
- Clocking blocks
2. Object Oriented Programming and Randomization
- OOP Basics
- Classes - Objects and handles
- Polymorphism and Inheritance
- Randomization
- Constraints
3. Threads and Virtual Interfaces
- Fork Join
- Fork Join_any
- Fork Join_none
- Event controls
- Mailboxes and semaphores
- Virtual Interfaces
- Transactors
- Building verification environment
- Testcases
4. Callbacks
- Facade Class
- Building Reusable Transactors
- Inserting Callbacks
- Registering Callbacks
5. Direct Programming Interface
6. Functional Coverage
- Coverage models
- Cover points and bins
- Cross coverage
- Regression testing
Advanced SystemVerilog
- Environment Configuration
- Reference Models and Predictor Logics
- Using Legacy BFMs
- Scenario Generation
- Testcases - Random, Directed and corner case
- Co
- Environment Configuration
- Reference Models and Predictor Logics
- Using Legacy BFMs
- Scenario Generation
- Testcases - Random, Directed and corner case
- Coding styles for VIP
UVM – Universal Verification Methodology
- Introduction to UVM Methodology
- Overview of Project
- UVM TB Architecture
- Stimulus Modeling
- Creating UVCs and Environment
- UVM Simulation Phases
- Testcase Classes
- TLM Overview
- Configuring TB Environment
- UVM Sequencers
- Connecting DUT- Virtual Interface
- Virtual Sequences and Sequencers
- Creating TB Infrastructure
- Connecting multiple UVCs
- Building a Scoreboard
- Introduction to Register Modeling
- Building reusable environments
Verification Mini Project
- Verification and RTL sign-off
- Project specification analysis
- Defining verification plan
- Creating Testbench architecture
- Implementing the transactors - Generator, Driver, Receiver, and Scoreboard
- Defining Transaction
- Implementing the coverage model
- Building the top-level verification environment
- Building the regression test suite
- Coverage Analysis and Coverage Closure
Interfaces and Protocols
Lectures by Industry Experts
Verification Planning and Management
- Verification Plan
- TB Architecture
- Coverage Model
- Tracking the simulation process
- Building regression test suite
- Testsuite optimization
Assertion Based Verification – SVA
- Introduction to ABV
- Immediate Assertions
- Simple Assertions
- Sequences
- Sequence Composition
- Advanced SVA Features
- Assertion Coverage
Business communication
- The transition from College to Corporate
- Interpersonal skills and Presentation Skills
- Email Etiquette
- Resume writing
- Mockup Interviews Technical/HR
- Interview Skills: Group Discussion and HR Round Preparation
ELECTIVE MODULE | Design for Testability – DFT
Design for Testability - DFT
- Introduction to DFT
- Types of Testing
- Basic Testing Principles
- Fault Collapsing
- Introduction to Tessent Shell
- Structured Techniques
- BIST & Boundary scan
- DFT Techniques - Ad-hoc Techniques
- Scan Chain
- Test Coverage
- Fault Change
- Tessent Shells
- System Modes & TSDB
RISC-V Processor
1. RISC-V Instruction Set Architecture
- RISC-V processor overview
- RISC-V ISA Overview
- RV32I - R and I Type Instruction
- RV32I - S and B Type Instructions
- RV32I- J and U Type Instructions
- RV32I- Assembly Programs
2. RISC-V RV32I RTL Architecture Design
- RISC-V Execution Stages and Flow
- RISC-V Register File and RV32I Instructions Format
- RV32I — R and I Type ALU Datapath
- RV32I- S Type ALU Datapath - Load and Store
- RV32I- B and U Type ALU Datapath
- RV32I- J Type ALU Datapath - JAL and JALR
3. RISC-V RV32I 5 stage Pipelined RTL Design
- CPU Performance and RISC-V 5 Stage Pipeline Overview
- RISC-V 5 Pipeline - Data Hazards and Design Approach
- RISC-V 5 Stage Pipeline - Control Hazards and Design Approach
Industry Standard Project
- Design specification analysis
- Creating the design architecture
- Partitioning the design
- RTL coding in Verilog
- RTL functional verification
- RTL Synthesis
- Building regression test suite
- Coverage Analysis and Coverage Closure
Your Instructors
Google