About This Course
This hands-on training course provides an in-depth understanding of the RISC-V ISA and pipeline RISC-V processor RTL design architecture. You’ll learn how to effectively verify RISC-V Verilog RTL designs using the Universal Verification Methodology (UVM). Through practical exercises, Quantum Academy will guide you through the verification process, helping you build the skills needed to ensure the robustness and functionality of your RISC-V designs.
Course Curriculum
UVM – Stimulus Modelling & Testbench Overview
- UVM Stimulus Modelling – Predefined Methods and Field Registration Process
- UVM Stimulus Modelling – Overriding the predefined do_ methods
- UVM – TB Overview
- Knowledge Check – UVM Stimulus Modelling & TB Overview
UVM Phases & Reporting Mechanism
- UVM Phases – Necessity of Phases & pre-run Phases
- UVM Phases – Run Phase, post-run Phases and Objection Mechanism
- UVM Reporting Mechanism
- Knowledge Check – UVM Phases & Reporting Mechanism
UVM TLM Ports and Configuration
- UVM TLM Ports – Blocking put and get ports
- UVM TLM Ports – TLM FIFO and Analysis Ports
- UVM Configuration – Introduction to Configuration Facility
- UVM Configuration – Configuration class and Configuration of Virtual Interface
- Knowledge Check – UVM TLM Ports and Configuration
UVM – Creating UVM Testbench Components
- Creating UVM TB Components – Sequencers & Drivers
- Creating UVM TB Components – Monitor, Agents, Env and Testcases
- Knowledge Check – UVM – Creating UVM Testbench Components
UVM Sequences
- UVM Sequences – Introduction and Sequence item flow
- UVM Sequences – Starting the sequences and Default Sequence
- Knowledge Check – UVM Sequences
UVM – Virtual Sequences & Virtual Sequencers
- UVM Virtual Sequences & Virtual Sequencers – Introduction
- UVM Virtual Sequences & Virtual Sequencers – implementation
- \Knowledge Check – UVM – Virtual Sequences & Virtual Sequencers
UVM Callbacks & Events
- UVM Callbacks
- UVM Events
- Knowledge Check – UVM Callbacks & Events
UVM – Creating Scoreboard
- UVM Creating Scoreboard
- Knowledge Check – UVM – Creating Scoreboard
UVM – Register Abstraction Layer
- UVM RAL – Adapter, Predictor and Integration
- UVM RAL – Definition of Register Sequences
- UVM RAL – Intro & Definition of Register Block
- Knowledge Check – UVM RAL
UVM – CaseStudies
- Advanced_UVM_CaseStudies
UVM Lab Setup guide – reference manuals
- UVM Labs User Guide
- VPN Configuration Guide
UVM Labs
- UVM Lab Manual
- Lab1 Solution : Stimulus Modeling
- Lab2 Solution : Factory Overriding
- Lab3 Solution : UVM Phases
- Lab4 Solution : Creating UVM agent
- Lab5 Solution : UVM Sequences
- Lab6 Solution : Virtual Interface
- Lab7 Solution : Agent Integration
- Lab8 Solution : UVM Socreboard
- Lab9 Solution : SoC – UVM VE implementation
- Lab10 Solution : Coverage & Regression
RISC-V Processor Verification
- RISC-V Verification Plan-1
- RISC-V Verification Plan -2
- RISC-V TB Architecture
Curriculum
30 Lessons
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 – (Introduction to Various ISA’s and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 (introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RISC-V RV32I Processor
RISC-V RV32I 5 Stage Pipeline Processor
Linux Operating System
Universal Verification Methodology Overview
UVM Reference Guide
UVM TB Architecture and Base Class Hierarchy
UVM Factory
Your Instructors
Google