About This Course
Take your career to the next level by turning your ambitions into reality
What is VLSI VM?
The Advanced ASIC Verification course [VLSI VM] provides in-depth training on verification methodologies, preparing engineers to enter the industry as skilled ASIC Verification Engineers. Key features of the course include:
- ASIC Verification Methodologies
- Advanced Verilog for Verification
- SystemVerilog and UVM (Universal Verification Methodology)
- Assertion-Based Verification (SVA)
- Verification Planning and Management
- Code and Functional Coverage
- Perl Scripting for Automation
- VIP (Verification IP) Coding Style
This comprehensive curriculum ensures that students gain the knowledge and hands-on experience necessary to excel in ASIC verification roles, equipping them with the latest tools and techniques used in the industry.
Why join VLSI VM?
The role of a verification engineer in the VLSI industry requires a blend of technical expertise in digital design and verification methodologies, along with strong problem-solving and collaboration skills.
As chip designs become more complex, VLSI verification has evolved into a highly specialized field that demands in-depth knowledge of both digital design and cutting-edge verification techniques. This advanced ASIC Verification course, with 100% placement assistance, offers top-tier training in the latest verification skills, including **SystemVerilog**, **Assertion-Based Verification (SVA)**, and **UVM**. The course also provides valuable industry experience through an internship, ensuring that graduates are well-prepared and ready to step into the role of an ASIC Verification Engineer.
Blended Course
5 Months Training + 6 Months Internship
Theory & Labs: 3 months, Online course with daily live Q&A support
Projects: 2 months: Offline / Online
Internship: 6 months, Offline / Online
Weekend Course
8 Months Training + 6 Months Internship
Theory & Labs: 6 months, Online course with live Q&A support on weekends
Projects: 2 months, Offline / Online
Internship: 6 months, Offline / Online
Offline Course
5 Months Training + 6 Months Internship
Theory & Labs: 3 months, Offline Training
Projects: 2 months, Offline
Internship: 6 months, Offline
Online Course
Theory & Labs: Self-paced
Projects: Self-paced
Internship: Self-paced
Key Features
Course Features
- Training and Internship
- Advanced Logic Design
- ASIC Verification Methodologies
- Advanced Verilog for Verification
- HVL: SystemVerilog
- Verification Methodology: UVM
- Assertion-Based Verification: SVA
- Verification Planning and Management
- Code and Functional Coverage
- Scripting – Perl
- Coding styles for VIPs
- Pilot Projects
- Industry Standard Project
- Operating System – Linux
- RISC-V Instruction Set Architecture
- RISC-V RV32I RTL Architecture Design
Internship Projects
- AHB2APB Bridge RTL
- PCS Subsystem RTL design
- SPI IP core RTL Design
- UART IP core RTL Design
- AHB UVC – Master agent in UVM
- AHB2APB Bridge Verification in UVM
- UART IP Verification in UVM
- AHB UVC – Slave agent in UVM
- GPIO Verification in UVM
- PCS subsystem IP Verification – UVM
- AXI UVC – Master agent in UVM
- I2C Real Time Clock IP design
- ICPIT Verification in UVM
- AXI UVC – Slave agent in UVM
- SPI IP Verification – UVM
- RISC-V Verification in UVM
- Bluetooth VIP in UVM
Elective Modules
- DFT – Design For Testability
EDA Tools
- Siemens
- Synopsys
- Xilinx
- Aldec
VLSI VM Curriculum
Our Advanced VLSI Verification course offers exclusive training on cutting-edge, high-demand chip design technologies, complemented by an internship to provide real-world industry experience. The course features a dynamic learning approach, with a 30:70 ratio of theory to hands-on practice. The blend of classroom instruction and practical lab assignments and projects ensures that students not only learn key concepts but also gain the experience needed to apply them in real-world scenarios, solidifying their understanding.
Designed to align with the career goals of fresh engineering graduates, the course’s evolving curriculum equips students with the latest skills in semiconductor technology, helping them “future-proof” their careers and stay ahead in the rapidly changing VLSI industry.
Requirements
- BE/BTech in EEE/ECE/TE/CSE/IT/ Instrumentation + Good Knowledge of Verilog
- ME/MTech/MS in Electronics/MSc Electronics + Good Knowledge of Verilog
Curriculum
Advanced Digital
- Combinational Circuits - Design and Analysis
- Shift Registers and Counters
- Sequential Circuits - Design and Analysis
- Finite State Machine
Introduction to Linux
- Components of the UNIX system
- Directory Structure
- Utilities and Commands
- Vi Editor
Static Timing Analysis
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Methods to improve timing
Advanced Verilog for verification
- Tasks and Functions
- Race Conditions
- File I/O operation
- TB Constructs
- Self checking Testbenches
- Delays - Regular, Intra Assignment, and Inertial Delays
Code Coverage
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM - State, Arc, and Sequence coverage
Design Automation using Scripts – Perl
- Introduction to Perl
- Functions and Statements
- Numbers, Strings, and Quotes
- Comments and Loops
- Regular Expressions
- File Operations
ASIC Verification Methodologies
- Directed Vs Random
- Functional verification process
- Monitors and reference models
- Stimulus Generation
- Verification Planning and management
- Bus functional model
- Coverage Driven Verification
Business communication
- The transition from College to Corporate
- Interpersonal skills and Presentation Skills
- Email Etiquette
- Resume writing
- Mockup Interviews Technical/HR
- Interview Skills: Group Discussion and HR Round Preparation
SystemVerilog HVL
- New Data types
- Tasks and Functions
- Interfaces
- Clocking Blocks
- OOP Basics
- Classes - Objects and handles
- Polymorphism and Inheritance
- Randomization
- Constraints
- Fork Join
- Fork Join_any
- Fork Join_none
- Event controls
- Mailboxes and semaphores
- Virtual Interfaces
- Transactors
- Building verification environment
- Test cases
- Facade Class
- Building Reusable Transactors
- Inserting Callbacks
- Registering Callbacks
- Coverage models
- Cover points and bins
- Cross coverage
- Regression testing
Interfaces and Protocols
Advanced SystemVerilog
- Environment Configuration
- Reference Models and Predictor Logics
- Using Legacy BFMs
- Scenario Generation
- Test Cases - Random, Directed and
- Corner Case
- Coding styles for VIP
Assertion Based Verification – SVA
- Introduction to ABV
- Immediate Assertions
- Simple Assertions
- Sequences
- Sequence Composition
- Advanced SVA Features
- Assertion Coverage
UVM-Universal Verification Methodology
- Introduction to UVM Methodology
- Overview of Project
- UVM TB Architecture
- Stimulus Modeling
- Creating UVCs and Environment
- UVM Simulation Phases
- Testcase Classes
- TLM Overview
- Configuration TB Environment
- UVM Sequencers
- Connecting DUT - Virtual Interface
- Virtual Sequences and Sequencers
- Creating TB Infrastructure
- Connecting multiple UVCs
- Building a Scoreboard
- Introduction to Register Modeling
- Building reusable environments
Verification Planning and Management
- Verification Plan
- TB Architecture
- Coverage Model
- Tracking the simulation process
- Building regression test suite
- Testsuite optimization
Verification Mini Project
- Verification and RTL sign-off
- Project specification analysis
- Defining verification plan
- Creating Testbench architecture
- Implementing the transactors - Generator Driver, Receiver, and Scoreboard
- Defining Transaction
- Implementing the coverage model
- Building the top-level verification environment
- Building regression test suite
- Coverage Analysis and Coverage Closure
Industry Standard Project
- Design specification analysis
- Creating the design architecture
- Partitioning the design
- RTL coding in Verilog
- RTL functional verification
- RTL Synthesis
- Building regression test suite
- Coverage Analysis and Coverage Closure
RISC V Processor
- RISC-V processor overview
- RISC-V ISA Overview
- RV32I – R and I Type Instruction
- RV32I – S and B Type Instructions
- RV32I – J and U Type Instructions
- RV32I – Assembly Programs
- RISC-V Execution Stages and Flow
- RISC-V Register File and RV32I Instructions Format
- RV32I – R and I Type ALU Datapath
- RV32I – S Type ALU Datapath - Load and Store
- RV32I – B and U Type ALU Datapath
- RV32I – J Type ALU Datapath – JAL and JALR
- CPU Performance and RISC-V 5-Stage Pipeline Overview
- RISC-V 5 Stage Pipeline – Data Hazards and Design Approach
- RISC-V 5 Stage Pipeline – Control Hazards and Design Approach
ELECTIVE MODULE | Design for Testability – DFT
- Introduction to DFT
- Types of Testing
- Basic Testing Principles
- Fault Collapsing
- Introduction to Tessent Shell
- Structured Techniques
- BIST & Boundary Scan
- DFT Techniques - Ad-hoc
- Techniques
- Scan Chain
- Test Coverage
- Fault Change
- System Modes & TSDB
Your Instructors
Google