About This Course
Start your VLSI career in Physical Design & Verification with Excellent Placement Assistance
What is Physical Design & Verification?
Physical design is the process of developing the layout of an integrated circuit (IC), while VLSI verification ensures that the IC operates correctly. In physical design, the task involves positioning and routing transistors, interconnections, and other components on the substrate to form a functional IC. The aim is to create a layout that is compact, efficient, and satisfies all performance, power, and reliability specifications. On the other hand, VLSI verification focuses on validating the functionality and performance of the design. This includes verifying signal integrity, power integrity, and compliance with timing constraints. The goal of verification is to ensure that the IC meets all its required specifications and functions as intended.
Why Join Physical Design & Verification Course Training for VLSI Engineers?
VLSI physical design and verification are critical areas of expertise in the semiconductor industry, with a strong demand for professionals skilled in these fields. As the industry increasingly focuses on developing energy-efficient and eco-friendly chips, engineers must adopt innovative approaches to VLSI physical design that minimize power consumption and reduce environmental impact.
The field of VLSI physical design and verification is highly complex, with numerous factors to consider at each stage. A hands-on course in this domain offers a comprehensive introduction to the discipline, equipping students with a solid understanding of the entire process. By exploring the various steps involved, students will learn how to streamline design cycles and enhance chip performance, preparing them for the challenges of modern semiconductor design.
Blended Course
7 Months Training + 5 Months Internship
- Theory & Labs: 5 months, Online course with daily live Q&A support
- Projects: 2 months, Offline / Online
- Internship: 5 months, Offline / Online
Weekend Course
11 Months Training + 5 Months Internship
- Theory & Labs: 9 months, Online course with live Q&A support on weekends
- Projects: 2 months, Offline / Online
- Internship: 5 months, Offline / Online
Offline Course
7 Months Training + 5 Months Internship
- Theory & Labs: 5 months, Offline Training
- Projects: 2 months, Offline
- Internship: 5 months, Offline
Online Course
- Theory & Labs: Self-paced
- Projects: Self-paced
- Internship: Self-paced
Key Features
Course Features
- ASIC & FPGA Design Methodologies
- HDL: Verilog
- RISC-V Instruction Set Architecture
- Physical Synthesis
- PDK and SDC
- Floor-Planning and Placement
- Clock Tree Synthesis (CTS)
- Routing
- Static Timing Analysis (STA)
- Physical Verification (DRC and LVS)
- Tcl Scripting
- Perl and Python Scripting
- Industry Standard Project
- Business Communication
Sample Internship Projects
- Physical Design Implementation on RISC-V Core Design
- Physical Design Implementaion on RISC-V SoC Design
- Physical Verification on RISC-V Core Design
- Physical Verification on RISC-V SoC Design
Elective Module
SystemVerilog for Design
EDA Tools
- Siemens
- Synopsys
- Xilinx
- Aldec
VLSI PD Curriculum
Our VLSI Physical Design & Verification course gives you the opportunity to gain hands-on experience with key implementation and sign-off steps in the back-end flow, from RTL to GDS-II. You’ll work on critical tasks such as Physical Synthesis, Floor-Planning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, and perform LVS (Layout Versus Schematic) and DRC (Design Rule Checking). By using industry-standard EDA tools throughout the course, you’ll develop the skills and expertise needed to become industry-ready and excel in VLSI design and verification.
Requirements
- BE/BTech in EEE/ECE/TE/CSE/IT/ Instrumentation
- ME/MTech/MS in Electronics/MSc Electronics
Curriculum
Introduction to VLSI
- VLSI Design Flow
- ASIC vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
- VLSI Design Flow Steps - Demo
Introduction to Physical Design
- Partitioning
- Floorplan & Powerplan
- Placement
- Static Timing Analysis (Signal Integrity and Cross Talk Issues)
- Clock Tree Synthesis
- Routing
- Physical Verification & Design Signoff
Advanced Digital Design
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits - Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits - Design and Analysis
- Memories and PLD
- Finite State Machine
Introduction to Linux
- Components of the UNIX system
- Directory Structure
- Utilities and Commands
- Vi Editor
Verilog HDL – RTL Coding and Synthesis
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
- Type Concept
- Nets and registers
- Non hardware equivalent variables
- Arrays
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
- System Tasks
- Internal variable monitoring
- Compiler directives
- File input and output
- Registers in Verilog
- Unwanted latches
- Operator synthesis
- RTL Coding style
Verilog Mini Project – RTL Coding
- Project Specification Analysis
- Understanding the architecture
- Module-level implementation and verification
- Building the top-level module
Design for Testability – DFT
- Introduction to DFT
- Types of Testing
- Basic Testing Principles
- Fault Collapsing
- DFT Techniques - AD-hoc Techniques
- Structured Techniques
- BIST & Boundary scan
- Introduction to Siemens EDA's Tessent Shell
CMOS Devices and Technology
- MOSFET Operation and Characteristics
- Non-ldeal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS Circuit design
- Transistor sizing & Scaling
- Layout and Stick Diagrams
- CMOS Processing Steps
- IC Fabrication
- Advancements in CMOS Technology - Current Trends
Python Scripting
- Introduction to Python
- Python Data Types
- Numerical Datatypes
- Boolean Datatypes
- String Datatypes
- List Datatypes
- Tuple
- Dictionaries
- Set Datatypes
- Python Operators
- Python Functions
- Python Conditional & loops
- Python Object Oriented Programming
- Python Exceptions
- Python File IO Operations
- Python Modules Abstraction levels
Tcl/Tk Scripting
- Tcl overview
- Tcl vs Perl
- Evaluating TCL scripts under Unix
- TcI syntax
- Datatypes
- Operators
- Branching & looping construct
- Subroutines
- File operations
- Regular expressions
- Special variables
- Built-in functions
- Introduction to Tk graphics
Static Timing Analysis
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Timing Closure
- Timing ECO's for each type of violation
- What is hierarchical timing closure - time budgeting and clocking
Floor Planning
- What is FLOOR PLANNING ?
- Several criteria used to measure the quality of Floorplans
- Inputs required
- How to qualify for Import Design?
- What is required to come with a good floor plan?
- How to do floor planning for planning Macros?
- Floorplan Steps
- How to qualify for Floorplan?
- Power planning
- Analyze QOR, Timing, congestion, area, and power
- Hierarchical floor planning and design partitioning
- I/O planning and RDL routing
Placement
- Introduction
- Different criteria driving the placement process
- Different tasks in placement
- Goals of placement
- Sanity checks before placement
- Placement algorithms
- Pre-placement
- Optimization techniques
- Placement qualification
- Analyze QOR, Timing, congestion, area, and power
Clock Tree Synthesis
- Sanity checks need to be done before CTS Preparations
- Difference between High Fan-out Net Synthesis (HFNS) & Clock Tree Synthesis
- Concurrent Clock and Data Optimization
- What is the difference between clock buffer and normal buffer?
- CTS Goals
- Clock Tree Design Rule Constraints
- Clock Tree Exceptions
- NDRs
- Analyze QOR, Timing, congestion, area, and power
Design Synthesis & PDKs
- Introduction to Synthesis
- Physical Synthesis
- Standard input and output files for a Synthesis tool
- How to Write SDC?
- How to analyse the synthesis report?
- LEC
- UPF
- PDK (.lib .lef .tf .ptf .rlc .ndm .dlib Milkyway, tlup files )
- Tool related Technology files
Physical Verification & Sign-off
- Design Rule Check (DRC)
- Typical DRC rules
- Layout versus Schematic (LVS)
- How LVS works
- Commonly faced LVS issues
- IR Drop Analysis
- Electro Migration
- Methods to fix EM
- PERC
- Signoff
Routing
- Sanity checks
- Routing flow (Global routing, Track assignment, Detailed Routing, Search and repair)
- Goals of Routing
- Routing Constraints
- Post Routing Optimization
- Analyze QOR, Timing, congestion, area, and power
Business Communication
- Transition from College to Corporate
- Interpersonal skills and Presentation Skills
- Email Etiquette
- Resume writing
- Interview Skills: Group Discussion & HR Round Preparation
- Mockup Interviews Technical/HR
Signal Integrity and Cross-Talk Issues
- Signal Integrity
- Concerns addressed by signal integrity
- Factors affecting signal integrity
- Cross Talk Noise
- Cross Talk Delay
- Antenna Effects
Industry Standard Projects
- Design specification analysis
- Creating the design architecture
- Partitioning the design
- RTL coding in Verilog
- RTL functional verification
- RTL Synthesis
- Place & Route the netlist
- Static Timing Analysis & ECO
- Physical Verification & Signoff
ELECTIVE MODULE | SystemVerilog for Design
- Introduction
- Data Types
- Packages
- Arrays
- SV Tasks & Functions
- SV Procedural Blocks
- SV Operators
- Unique/Priority case/if
- Interface
- Practical exercises on synthesis using design compiler
Your Instructors
Google