About This Course
What is VLSI DFT?
Design for testability in VLSI is a design technique that makes testing a chip possible. Design for Testability in VLSI is the extra logic put in the normal design, during the design process, which helps its post-production testing.
Why Join VLSI DFT Training for VLSI Engineers?
The VLSI-DFT course can help you build your skill set and get a job in the Semiconductor Industry
DFT in VLSI is a leading career choice these days as it involves architecture definition, logic design, verification, test pattern generation, and more.
By specializing in VLSI DFT, an engineering graduate can increase their chances of landing a specialized and high-paying job in the semiconductor industry.
VLSI DFT is a crucial aspect of modern chip design and testing, and a fresh engineering graduate who is knowledgeable in this area will have a competitive edge in the job market. Our engineers also work on multiple industry-standard projects that use the SoC protocols and gain real-time project experience through our internship program.
Blended Course
6 Months Training + 6 Months Internship
- Theory & Labs: 4 months, Online course with daily live Q&A support
- Projects: 2 months, Offline / Online
- Internship: 6 months, Offline / Online
Online Course
Theory & Labs: Self-paced
Projects: Self-paced
Internship: Self-paced
Key Features
Course Features
- ASIC & FPGA Design Methodologies
- Training and Internship
- Advanced Logic Design
- FPGA Architecture
- Verilog HDL
- Design for Testability – DFT
- RISC-V Instruction Set Architecture
- RISC-V RV32I RTL Architecture Design
- Static Timing Analysis
- Scripting Language: Perl
- Operating System – Linux
- Industry Standard Project
Sample Internship Projects
- RISC-V RTL Design
- RISC-V SoC Design
- AHB2APB Bridge RTL Design
- PCS Subsystem RTL Design
- SPI IP core RTL Design
- UART IP core RTL Design
- I2C Real-Time Clock IP design
- Insertion of DFT components in RISC-V Core Design
- Insertion of DFT components in RISC-V SoC Design
Elective Module
- SystemVerilog
EDA Tools
- Siemens
- Synopsys
- Xilinx
- Aldec
VLSI DFT Curriculum
We offer exclusive training on niche and high-in-demand chip design technology along with an Internship through Advanced VLSI Design and DFT Course. This course consists of smart classes and hands-on practice in a ratio of 30:70. Imbibing the methods in the class and applying them in through lab assignments and projects cements the concepts forever. The dynamic curriculum of the Advanced VLSI Design and DFT Course fits perfectly with the career aim of fresh engineering graduates and helps them to ‘future-proof’ themselves and remain relevant in the rapidly evolving Semiconductor technology space.
Requirements
- BE/BTech in EEE/ECE/TE/CSE/IT/ Instrumentation
- ME/MTech/MS in Electronics/MSc Electronics
Curriculum
Introduction to VLSI
- VLSI Design Flow
- ASIC Vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
- VLSI Design Flow Steps - Demo
Introduction to Linux
- Components of the UNIX system
- Directory Structure
- Utilities and Commands
- Vi Editor
Advanced Digital Design
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits - Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits - Design and Analysis
- Memories and PLD
- Finite State Machine
- Microcontroller Design
Static Timing Analysis
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Methods to improve timing
FPGA Architecture
- General Structure and Classification
- CPLD Vs FPGA
- Block Diagram of CPLD
- Detailed study of each block
- Timing Model
- FPGA Architecture
- CLBs and Input/Output Blocks
- Luts, SLICE DFFs
- Dedicated MUXes
- Programmable Interconnects
- Architectural Resources
- Power Distribution and Configuration
Verilog HDL – RTL Coding and Synthesis
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
- Type Concept
- Nets and registers
- Non-hardware equivalent variables
- Arrays
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
- System Tasks
- Compiler directives
- Internal variable monitoring
- File input and output
- Unwanted latches
- Operator synthesis
- Style Registers in Verilog
- RTL Coding style
CMOS Fundamentals
- Non-Ideal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS circuit design
- Fabrication Process Overview
- Transistor sizing
- Layout and Stick Diagrams
- CMOS Technology - Current Trends
- CMOS Processing Steps
Design Automation using Scripts – Perl
- Introduction to Perl
- Functions and Statements
- Numbers, Strings, and Quotes
- Comments and Loops
- Regular Expressions
- File Operations
Code Coverage
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM - State, Transition coverage
Verilog Mini Project RTL Coding and Synthesis
- Project Specification Analysis
- Understanding the architecture
- Module-level implementation and verification
- Building the top-level module
Design for Testability – DFT
- Introduction to DFT
- Importance of Testing
- Outcome of Testing
- ASIC Design Flow & Testing
- Verification Vs Testing
- Defect Vs Fault
- Types of Testing
- Testing at different Abstraction Levels
- Fault Modelling and Collapsing
- ATPG Basics
- Combinational ATPG
- Tessent Shell Introduction
- Fault Class
- Fault Simulation
- Tessent Shell Usage
- Additional Fault Models
- Scan Chain Insertion
- Test Compression
- Boundary Scan
- Introduction to BIST
- Logic BIST
- Memory BIST
- Design Rule Checks
- How to Improve Test Coverage
- Fault Diagnosis
- DFT logic implementation on a RISC -V Processor Design
DFT Pilot Project
- Implementing the DFT flow on Router Design
- Implementing the Design
- Generating the gate- level netlist
- Boundary- scan insertion
- Scan chain insertion
- EDT IP core insertion
- Test pattern generation
- Fault simulation Test
- Fault coverage analysis
RISC V Processor
- RISC-V processor overview
- RISC-V ISA Overview
- RV32I – R and I Type Instruction
- RV32I – S and B Type Instructions
- RV32I – J and U Type Instructions
- RV32I – Assembly Programs
- RISC-V Execution Stages and Flow
- RISC-V Register File and RV32I Instructions Format
- RV32I – R and I Type ALU Datapath
- RV32I – S Type ALU Datapath - Load and Store
- RV32I – B and U Type ALU Datapath
- RV32I – J Type ALU Datapath – JAL and JALR
- CPU Performance and RISC-V 5-Stage Pipeline Overview
- RISC-V 5 Stage Pipeline – Data Hazards and Design Approach
- RISC-V 5 Stage Pipeline – Control Hazards and Design Approach
Business communication
- The transition from College to Corporate
- Email Etiquette
- Interpersonal skills and Presentation Skills
- Resume writing
- Interview Skills: Group Discussion and HR Round Preparation
- Mockup Interviews Technical/HR
Industry Standard Project
- Implementing the DFT on RISC-V processor Design
- Generating the gate-level netlist
- Boundary-scan insertion
- Scan chain insertion
- EDT IP core insertion
- Test pattern generation
- Fault simulation
- Test & Fault coverage analysis
- Improve Test Coverage
Interfaces and Protocols
ELECTIVE MODULE | ASIC Verification Methodologies
- Directed Vs Random
- Functional verification process
- Stimulus Generation
- Bus function model
- Monitors and reference models
- Coverage Driven Verification
- Verification Planning and management
- New Data types
- Tasks and Functions
- Interfaces
- Clocking blocks
- OOP Basics
- Classes - Objects and handles
- Polymorphism and Inheritance
- Randomization
- Constraints
- Fork Join
- Fork Join_any
- Fork Join_none
- Event controls
- Mailboxes and semaphores
- Virtual Interfaces
- Transactors
- Building verification environment
- Test Cases
- Facade Class
- Building Reusable Transactors
- Inserting Callbacks
- Registering Callbacks
- Coverage models
- Cover points and bins
- Cross coverage
- Regression testing
Your Instructors
Google