About This Course
What is VLSI Verification Course?
The VLSI Verification Course at Quantum Academy begins with a solid introduction to functional verification techniques and the SystemVerilog language. It then delves into the details of constructing class-based verification environments using SystemVerilog HDVL. As part of the SystemVerilog for Verification module, the course trains you thoroughly in building test benches using object-oriented programming, applying constraint-random simulation, and achieving verification sign-off through functional coverage. It also introduces the UVM methodology and highlights the importance of using industry-standard practices like UVM to develop SystemVerilog-based test benches.
Why Join the VLSI Verification Course?
Unlike typical training programs or textbook-based courses, Quantum Academy’s VLSI Verification Course offers a hands-on, industry-relevant approach. The course revolves around a standard testbench architecture that not only supports SystemVerilog-based test benches but can also be easily extended into the UVM framework. Throughout the course, we use two real-world design examples to demonstrate key verification concepts. A dual-port RAM RTL design is used to explain core language features and testbench development techniques in detail, while a more advanced SoC design showcases how to handle complex verification scenarios and transition from IP-level to SoC-level test environments. This course is ideal for electronics engineers with a solid understanding of RTL design using Verilog HDL who are looking to build strong, practical skills in verification using SystemVerilog and UVM.
Key Features
- Case-Study Based Learning
- Upgrade to Advanced ASIC Verification Course [VLSI VM] with placement assistance
- Online course with Support Material
- Course Delivered by Industry Experts
- Power to ace job interviews
- Mobile Apps – Attend Anywhere Anytime
- Certificate on successful completion of the course
- Inexpensive Online VLSI Course
VLSI Verification Course Curriculum
The curriculum at Quantum Academy begins with a comprehensive introduction to functional verification techniques and the SystemVerilog language. It then guides you through the process of building class-based verification environments using SystemVerilog HDVL. Within the SystemVerilog for Verification module, you’ll gain hands-on experience in developing test benches through object-oriented programming, leveraging constraint-random simulation, and achieving verification sign-off via functional coverage. The course concludes with a deep dive into UVM methodology, emphasizing the importance of adopting IEEE-standard practices like UVM for creating scalable SystemVerilog-based test benches.
Curriculum
Module – 1 | ASIC Verification Methodologies
Directed Vs Random
Functional verification process
Stimulus Generation
Bus functional model
Monitors and reference models
Coverage Driven Verification
Verification Planning and management
Module – 2 | Introduction to SystemVerilog
New Data types
Tasks and Functions
Interfaces
Clocking blocks
1. Object Oriented Programming and Randomization
OOP Basics
Classes - Objects and handles
Polymorphism and Inheritance
Randomization
Constraints
2. Threads and Virtual Interfaces
Fork Join
Fork Join _ any
Fork Join _ none
Event controls
Mailboxes and semaphores
Virtual Interfaces
Transactors
Building verification environment
Testcases
3. Callbacks
Facade Class
Building Reusable Transactors
Inserting Callbacks
Registering Callbacks
4. Direct Programming Interface
5. Functional Coverage
Coverage models
Coverpoints and bins
Cross coverage
Regression testing
Module – 3 | Universal Verification Methodology Overview
Introduction to UVM
UVM Concepts
UVM SoC TB
UVM AHB UVC
UVM SoC TB Examples
Module – 4 | Case Study 1 : Dual Port RAM – SystemVerilog TB
Verification Plan
Testbench Architecture and Verification Flow
Transaction and Generator
Interface and Drivers
Monitors
Scoreboard and Reference Model
Environment and Testcases
Module – 5 | Case Study 2 : Quantum Academy SoC – SystemVeriIog TB
Quantum Academy SoC SystemVerilog Verification Environment
Your Instructors
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